Semiconductor products, such as integrated circuit chips, are typically fabricated in large numbers on a single semiconductor body (i.e., a wafer). Fabrication using a single semiconductor body allows manufacturers using larger wafers to increase throughput while decreasing the cost of fabricating an individual chip.
FIG. 1A shows an example integrated circuit chip wafer 100. On the wafer 100, individual chips or dies are fabricated in a repeating pattern adjacent to one another and across the wafer. After the front end of the line and back end of the line processing steps are completed, the wafer 100 is divided, along kerf lines 102, into a number of individual chips or dies 104. Each of the dies 104 is subsequently integrated into a package by wire bond or flip chip connections. The package provides the chip protection, heat dissipation, and connections to the outside world.
The division of an integrated circuit chip wafer 100 into individual dies 104 is usually termed “dicing” or “sawing” the wafer. Dicing the wafer 100 is usually done using a resin-bonded diamond saw to cut along the kerf lines 102. During such sawing, the integrated circuit chip wafer 100 undergoes stress. The stress of dicing frequently damages the outer regions of the die 104 adjacent to the kerf lines 102. The damage can generate micro-cracks in the semiconductor substrate or cause delamination between the interface of the substrate and an overlying dielectric layer or between any of the overlying dielectric and metallization layers. If proper protection is not employed on the chip, micro-cracks or delamination will propagate into the electrically active regions of a chip. In the active region micro-cracks or delamination can expose metal lines and dielectric materials to ambient environment, causing corrosion and oxidation of metallization levels, thereby damaging circuitry, lowering production yield, and, most problematically, potentially inducing product failures out in the field.
Damage to the dies from dicing is an increasing problem as minimum feature sizes continue to shrink. Chip manufacturers have struggled to continue to meet the scaling demands of emerging technology nodes to which designs are driven by the industry and Moore's law. To meet the scaling demands, emerging technologies have begun to widely use low-k and ultra low-k (ULK) dielectric materials. Such low-k dielectric materials allow tighter pitch on metal and contact levels without substantially raising the capacitance associated with the back end of the line metallization. However, such low-k dielectric materials do not provide the same degree of mechanical support offered by higher k dielectric materials. Therefore, the increased use of mechanically weaker low-k dielectric materials indicates an increased risk towards crack generation during and propagation after wafer dicing.
FIG. 1B shows the different regions of a single integrated circuit chip die 104. In an integrated circuit chip die 104, the active circuitry 106 is located in the central part of the die. To prevent micro-crack propagation, protection structures called scribe seals are designed and placed in a scribe seal region 108 located along the outer border or periphery of the die 104. Traditionally, scribe seal structures have been employed to prevent large cracks from entering into the active circuitry 106 of the integrated circuit chip. Accordingly, scribe seal integrity loss has focused on large scale damage that is often detected through visual inspection. Finite element simulations are also used to determine how cracks will propagate through the die. However, the use of such methods identifies only gross levels of damage, and is not sensitive enough to do statistically meaningful reliability characterization.
Therefore, there is a need for a method and structure that allows statistically relevant reliability characterization of scribe seal damage.